1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device for reducing an area of a refresh logic circuit that prevents the data deterioration of a memory cell caused by the disturbance of word lines.
2. Description of the Related Art
In general, a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) includes tens of millions of memory cells, and stores and outputs data in response to a command requested from a chipset. That is, if the chipset requests a write operation to the semiconductor memory device, the semiconductor memory device stores data on a memory cell corresponding to an address inputted from the chipset, and if the chipset requests a read operation to the semiconductor memory cell, the semiconductor memory device outputs the data stored on the memory, cell corresponding to the address inputted from the chipset.
A group of memory cells is referred to as a memory bank. The number of memory banks may be changed according to a design of the semiconductor memory device.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, a conventional semiconductor memory device 1000 includes a plurality of bank groups. Each 100 of the plurality of bank groups includes four memory banks 110A, 110B, 110C and 110D, two row control regions 120 and 130, four column control regions 140A, 1406, 140C and 140D, and two refresh control units 150 and 160. Each of the four memory banks 110A, 110B, 110C and 110D includes a plurality of memory cells. The two row control regions 120 and 130 and four column control regions 140A, 140B, 140C and 140D correspond to the four memory banks 110A, 110B, 110C and 110D. For reference, the two row control regions 120 and 130 include circuits for controlling a row access of the four memory banks 110A, 110B, 110C and 110D. The four column control regions 140A, 140B, 140C and 140D include circuits for controlling a column access of the four memory banks 110A, 1106, 1100 and 110D. The four memory banks 110A, 110B, 110C and 110D are disposed along a first direction in the conventional semiconductor memory device 1000.
As the integration of memory cells are increased, an interval among a plurality of word lines included in the conventional semiconductor memory device is reduced. As the interval among the word lines is reduced, a coupling effect among adjacent word lines is increased. As the coupling effect among the adjacent word lines is increased, data of memory cells coupled to the word lines, which are frequently activated, are damaged. This is referred to as a word line disturbance. Due to word line disturbance, data of memory cells are damaged before the memory cells are refreshed. Thus, a target row refresh (TRR) operation is performed to prevent the word line disturbance. The TRR operation represents that when a target word line having large or frequent number of active-precharges is detected, the memory cells coupled to the adjacent word lines are refreshed. The refresh control units 150 and 150 activate the word lines corresponding to a target row address, which is applied in response to control signals CTRL_SIGs, e.g., an active command, during a target row refresh mode. Since the refresh control units 150 and 160 are disposed closely to the row control regions 140A, 140B, 140C and 140D, the refresh control units 150 and 160 perform an operation related to a row region of the memory banks 110A, 110B, 1100 and 110D. Moreover, since the four memory banks 110A, 110B, 110C and 110D are disposed along a first direction in each 100 of the bank groups of the conventional semiconductor memory device 1000, two refresh control units 150 and 160 are necessary. However, as the integration of a semiconductor memory device is increased, a plurality of refresh control units are disposed in each of the plurality of bank groups, and the area of the plurality of refresh control units are increased.
FIG. 2 is a diagram illustrating a target row refresh operation of the conventional semiconductor memory device.
In general, a semiconductor memory device includes a plurality of word lines. A semiconductor controller provides command signals CMDs, addresses ADDs and data to the semiconductor memory device, and controls the semiconductor memory device. If a word line having large or frequent number of active-precharges is frequently access, memory cells coupled to adjacent word lines are affected. That is, data of the memory cells may be damaged. Thus, the TRR operation may be performed to overcome above-mentioned problem.
Referring to FIG. 2, through the TRR operation, the deterioration of memory cells caused by the word line disturbance is prevented by detecting a word line having a frequent access and performing a refresh operation on the adjacent word lines. The semiconductor memory device or the semiconductor controller detects a target row address of the target word line having large or frequent number of active-precharges. If the target row address is detected, the semiconductor controller provides the command signals CMDs and the addresses ADDs for instructing a target active operation of the semiconductor memory device. If the semiconductor memory device is set to the TRR mode by a mode register set (MRS), after the active-precharge command for the TRR operation is applied three times the TRR mode exits. The target row address “N” is applied to the semiconductor memory device in response to a first active command signal ACT, and a precharge command signal is applied to the semiconductor memory device after a predetermined time elapses. The semiconductor memory device activates and precharges the target word line corresponding to the target row address “N”. Subsequently, a second active command signal ACT is applied to the semiconductor memory device, a word line adjacent to the target word line is access in response to the second active command signal ACT, and a precharge operation is performed. Next, a third active command signal ACT is applied to the semiconductor memory device, another word line adjacent to the target word line is access in response to the third active command signal ACT, and the TRR operation is performed.
A refresh operation must be performed through an active-precharge operation of the word line corresponding to the target row address “N”, and adjacent word lines thereto. Thus, a target row counter for receiving and counting the target row address “N”, and generating addresses corresponding to the adjacent word lines is needed.